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| the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local elpida memory, inc. for availability and additional information. mos integrated circuit pd45128441, 45128841, 45128163 128m-bit synchronous dram 4-bank, lvttl data sheet document no. e0031n30 (ver. 3.0) date published august 2001 cp (k) printed in japan elpida memory, inc. is a joint venture dram company of nec corporation and hitachi, ltd. description the pd45128441, 45128841, 45128163 are high-speed 134,217,728-bit synchronous dynamic random-access memories, organized as 8,388,608 4 4, 4,194,304 8 4, 2,097,152 16 4 (word bit bank), respectively. the synchronous drams achieved high-speed data transfer using the pipeline architecture. all inputs and outputs are synchronized with the positive edge of the clock. the synchronous drams are compatible with low voltage ttl (lvttl). these products are packaged in 54-pin tsop (ii). features ? fully synchronous dynamic ram, with all signals referenced to a positive clock edge ? pulsed interface ? possible to assert random column address in every cycle ? quad internal banks controlled by ba0(a13) and ba1(a12) ? byte control ( 16) by ldqm and udqm ? programmable wrap sequence (sequential / interleave) ? programmable burst length (1, 2, 4, 8 and full page) ? programmable /cas latency (2 and 3) ? automatic precharge and controlled precharge ? cbr (auto) refresh and self refresh ? 4, 8, 16 organization ? single 3.3 v 0.3 v power supply ? lvttl compatible inputs and outputs ? 4,096 refresh cycles / 64 ms ? burst termination by burst stop command and precharge command
data sheet e0031n30 2 pd45128441, 45128841, 45128163 ordering information part number organization (word bit bank) clock frequency mhz (max.) package pd45128441g5-a75a-9jf 8m 4 4 133 54-pin plastic tsop (ii) pd45128441g5-a75-9jf 133 (10.16mm (400)) pd45128441g5-a80-9jf 125 pd45128441g5-a10-9jf 100 pd45128841g5-a75a-9jf 4m 8 4 133 pd45128841g5-a75-9jf 133 pd45128841g5-a80-9jf 125 pd45128841g5-a10-9jf 100 pd45128163g5-a75a-9jf 2m 16 4 133 pd45128163g5-a75-9jf 133 pd45128163g5-a80-9jf 125 pd45128163g5-a10-9jf 100 pd45128441g5-a75l-9jf 8m 4 4 133 pd45128441g5-a80l-9jf 125 pd45128841g5-a75l-9jf 4m 8 4 133 pd45128841g5-a80l-9jf 125 pd45128163g5-a75l-9jf 2m 16 4 133 pd45128163g5-a80l-9jf 125 data sheet e0031n30 3 pd45128441, 45128841, 45128163 part number pd45128841g5 - a75l interface 1 : lvttl number of banks 4 : 4 banks organization 4 : x4 8 : x8 memory density 128 : 128m bits synchronous dram nec memory package g5 : tsop (ii) low voltage a : 3.3 v 0.3 v minimum cycle time 75a : 7.5 ns (133 mhz @cl=2) 75 : 7.5 ns (133 mhz @cl=3) 80 : 8 ns (125 mhz) 10 : 10 ns (100 mhz) low power [ x4, x8 ] 163 [ x16 ] number of banks and interface 3 : 4 banks, lvttl organization 16 : x16 data sheet e0031n30 4 pd45128441, 45128841, 45128163 pin configurations /xxx indicates active low signal. [ pd45128441] 54-pin plastic tsop (ii) (10.16mm (400)) 8m words 4 bits 4 banks v cc nc v cc q nc dq0 v ss q nc nc v cc q nc dq1 v ss q nc v cc nc /we /cas /ras /cs ba0(a13) ba1(a12) a10 a0 a1 a2 a3 v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 vss nc vssq nc dq3 vccq nc nc vssq nc dq2 vccq nc vss nc dqm clk cke nc a11 a9 a8 a7 a6 a5 a4 vss 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 a0 to a11 note : address inputs ba0(a13), ba1(a12) : bank select dq0 to dq3 : data inputs / outputs clk : clock input cke : clock enable /cs : chip select /ras : row address strobe /cas : column address strobe /we : write enable dqm : dq mask enable v cc : supply voltage v ss : ground v cc q : supply voltage for dq v ss q : ground for dq nc : no connection note a0 to a11 : row address inputs a0 to a9, a11 : column address inputs data sheet e0031n30 5 pd45128441, 45128841, 45128163 [ pd45128841] 54-pin plastic tsop (ii) (10.16mm (400)) 4m words 8 bits 4 banks v cc dq0 v cc q nc dq1 v ss q nc dq2 v cc q nc dq3 v ss q nc v cc nc /we /cas /ras /cs ba0(a13) ba1(a12) a10 a0 a1 a2 a3 v cc vss dq7 vssq nc dq6 vccq nc dq5 vssq nc dq4 vccq nc vss nc dqm clk cke nc a11 a9 a8 a7 a6 a5 a4 vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 a0 to a11 note : address inputs ba0(a13), ba1(a12) : bank select dq0 to dq7 : data inputs / outputs clk : clock input cke : clock enable /cs : chip select /ras : row address strobe /cas : column address strobe /we : write enable dqm : dq mask enable v cc : supply voltage v ss : ground v cc q : supply voltage for dq v ss q : ground for dq nc : no connection note a0 to a11 : row address inputs a0 to a9 : column address inputs data sheet e0031n30 6 pd45128441, 45128841, 45128163 [ pd45128163] 54-pin plastic tsop (ii) (10.16mm (400)) 2m words 16 bits 4 banks v cc dq0 v cc q dq1 dq2 v ss q dq3 dq4 v cc q dq5 dq6 v ss q dq7 v cc ldqm /we /cas /ras /cs ba0(a13) ba1(a12) a10 a0 a1 a2 a3 v cc vss dq15 vssq dq14 dq13 vccq dq12 dq11 vssq dq10 dq9 vccq dq8 vss nc udqm clk cke nc a11 a9 a8 a7 a6 a5 a4 vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 a0 to a11 note : address inputs ba0(a13), ba1(a12) : bank select dq0 to dq15 : data inputs / outputs clk : clock input cke : clock enable /cs : chip select /ras : row address strobe /cas : column address strobe /we : write enable ldqm : lower dq mask enable udqm : upper dq mask enable v cc : supply voltage v ss : ground v cc q : supply voltage for dq v ss q : ground for dq nc : no connection note a0 to a11 : row address inputs a0 to a8 : column address inputs data sheet e0031n30 7 pd45128441, 45128841, 45128163 block diagram clock generator mode register command decoder control logic row address buffer & refresh counter column address buffer & burst counter data control circuit latch circuit input & output buffer dq dqm clk cke address /cs /ras /cas /we bank d bank c bank b sense amplifier column decoder & latch circuit bank a row decoder data sheet e0031n30 8 pd45128441, 45128841, 45128163 contents 1. input / output pin function ................................................................................................ ........... 10 2. commands ................................................................................................................... ................... 11 3. simplified state diagram ................................................................................................... ............ 14 4. truth table ................................................................................................................ ...................... 15 4.1 command truth table ........................................................................................................ .................... 15 4.2 dqm truth table ............................................................................................................ ......................... 15 4.3 cke truth table ............................................................................................................ .......................... 15 4.4 operative command table ................................................................................................... ................. 16 4.5 command truth table for cke ............................................................................................... .............. 19 5. initialization ............................................................................................................. ....................... 20 6. programming the mode register .............................................................................................. ... 21 7. mode register .............................................................................................................. .................. 22 7.1 burst length and sequence ................................................................................................. ................. 23 8. address bits of bank-select and precharge ............................................................................... 24 9. precharge .................................................................................................................. ...................... 25 10. auto precharge ............................................................................................................ ................... 26 10.1 read with auto precharge ................................................................................................. ................. 26 10.2 write with auto precharge ................................................................................................ .................. 27 11. read / write command interval ............................................................................................. ....... 28 11.1 read to read command interval ............................................................................................ ........... 28 11.2 write to write command interval .......................................................................................... ............. 28 11.3 write to read command interval ........................................................................................... ............ 29 11.4 read to write command interval ........................................................................................... ............ 30 12. burst termination ......................................................................................................... ................. 31 12.1 burst stop command ....................................................................................................... ................... 31 12.2 precharge termination .................................................................................................... ................... 32 12.2.1 precharge termination in read cycle ................................................................................... 32 12.2.2 precharge termination in write cycle ................................................................................. 3 3 data sheet e0031n30 9 pd45128441, 45128841, 45128163 13. electrical specifications ................................................................................................. ............... 34 13.1 ac parameters for read timing ............................................................................................ ............. 39 13.2 ac parameters for write timing ........................................................................................... ............. 41 13.3 relationship between frequency and latency ............................................................................... .. 42 13.4 mode register set ........................................................................................................ ....................... 43 13.5 power on sequence and cbr (auto) refresh ................................................................................. . 44 13.6 /cs function ............................................................................................................. ........................... 45 13.7 clock suspension during burst read (using cke function) ......................................................... 46 13.8 clock suspension during burst write (using cke function) ......................................................... 48 13.9 power down mode and clock mask ........................................................................................... ....... 50 13.10 cbr (auto) refresh ...................................................................................................... ....................... 51 13.11 self refresh (entry and exit) ........................................................................................... ................... 52 13.12 random column read (page with same bank) ............................................................................... 53 13.13 random column write (page with same bank) ............................................................................... 55 13.14 random row read (ping-pong banks) ....................................................................................... ...... 57 13.15 random row write (ping-pong banks) ...................................................................................... ...... 59 13.16 read and write .......................................................................................................... .......................... 61 13.17 interleaved column read cycle ........................................................................................... .............. 63 13.18 interleaved column write cycle .......................................................................................... ............... 65 13.19 auto precharge after read burst ......................................................................................... .............. 67 13.20 auto precharge after write burst ........................................................................................ ............... 69 13.21 full page read cycle .................................................................................................... ...................... 71 13.22 full page write cycle ................................................................................................... ....................... 73 13.23 byte write operation .................................................................................................... ....................... 75 13.24 burst read and single write (option) .................................................................................... ........... 77 13.25 full page random column read ............................................................................................ ........... 79 13.26 full page random column write ........................................................................................... ............ 81 13.27 pre (precharge) termination of burst .................................................................................... .......... 83 14. package drawing ........................................................................................................... ................ 85 15. recommended soldering conditions .......................................................................................... 86 16. revision history .......................................................................................................... ................... 87 data sheet e0031n30 10 pd45128441, 45128841, 45128163 1. input / output pin function pin name input / output function clk input clk is the master clock input. other inputs signals are referenced to the clk rising edge. cke input cke determine validity of the next clk (clock). if cke is high, the next clk rising edge is valid; otherwise it is invalid. if the clk rising edge is invalid, the internal clock is not issued and the pd45128xxx suspends operation. when the pd45128xxx is not in burst mode and cke is negated, the device enters power down mode. during power down mode, cke must remain low. /cs input /cs low starts the command input cycle. when /cs is high, commands are ignored but operations continue. /ras, /cas, /we input /ras, /cas and /we have the same symbols on conventional dram but different functions. for details, refer to the command table. a0 - a11 input row address is determined by a0 - a11 at the clk (clock) rising edge in the active command cycle. it does not depend on the bit organization. column address is determined by a0 - a9, a11 at the clk rising edge in the read or write command cycle. it depends on the bit organization: a0 - a9, a11 for 4 device, a0 - a9 for 8 device, a0 - a8 for 16 device. a10 defines the precharge mode. when a10 is high in the precharge command cycle, all banks are precharged; when a10 is low, only the bank selected by ba0(a13) and ba1(a12) is precharged. when a10 is high in read or write command cycle, the precharge starts automatically after the burst access. ba0, ba1 input ba0(a13) and ba1(a12) are the bank select signal. in command cycle, ba0(a13) and ba1(a12) low select bank a, ba0(a13) high and ba1(a12) low select bank b, ba0(a13) low and ba1(a12) high select bank c and then ba0(a13) and ba1(a12) high select bank d. dqm, udqm, ldqm input dqm controls i/o buffers. in 16 products, udqm and ldqm control upper byte and lower byte i/o buffers, respectively. in read mode, dqm controls the output buffers like a conventional /oe pin. dqm high and dqm low turn the output buffers off and on, respectively. the dqm latency for the read is two clocks. in write mode, dqm controls the word mask. input data is written to the memory cell if dqm is low but not if dqm is high. the dqm latency for the write is zero. dq0 - dq15 input / output dq pins have the same function as i/o pins on a conventional dram. v cc , v ss , v cc q, v ss q (power supply) v cc and v ss are power supply pins for internal circuits. v cc q and v ss q are power supply pins for the output buffers. data sheet e0031n30 11 pd45128441, 45128841, 45128163 2. commands mode register set command (/cs, /ras, /cas, /we = low) the pd45128xxx has a mode register that defines how the device operates. in this command, a0 through a11, ba0(a13) and ba1(a12) are the data input pins. after power on, the mode register set command must be executed to initialize the device. the mode register can be set only when all banks are in idle state. during 2 clk (t rsc ) following this command, the pd45128xx x cannot accept any other commands. fig.1 mode register set command /we /cas /ras /cs cke clk h add a10 ba0(a13), ba1(a12) activate command (/cs, /ras = low, /cas, /we = high) the pd45128xxx has four banks, each with 4,096 rows. this command activates the bank selected by ba0(a13) and ba1(a12) and a row address selected by a0 through a11. this command corresponds to a conventional dram?s /ras falling. fig.2 row address strobe and bank activate command /we /cas /ras /cs cke clk h add a10 ba0(a13), ba1(a12) row row precharge command (/cs, /ras, /we = low, /cas = high) this command begins precharge operation of the bank selected by ba0(a13) and ba1(a12). when a10 is high, all banks are precharged, regardless of ba0(a13) and ba1(a12). when a10 is low, only the bank selected by ba0(a13) and ba1(a12) is precharged. after this command, the pd45128xxx can?t accept the activate command to the precharging bank during t rp (precharge to activate command period). this command corresponds to a conventional dram?s /ras rising. fig.3 precharge command /we /cas /ras /cs cke clk h add a10 ba0(a13), ba1(a12) (precharge select) data sheet e0031n30 12 pd45128441, 45128841, 45128163 write command (/cs, /cas, /we = low, /ras = high) if the mode register is in the burst write mode, this command sets the burst start address given by the column address to begin the burst write operation. the first write data in burst mode can input with this command with subsequent data on following clocks. fig.4 column address and write command /we /cas /ras /cs cke clk h add a10 ba0(a13), ba1(a12) col. read command (/cs, /cas = low, /ras, /we = high) read data is available after /cas latency requirements have been met. this command sets the burst start address given by the column address. fig.5 column address and read command /we /cas /ras /cs cke clk h add a10 ba0(a13), ba1(a12) col. cbr (auto) refresh command (/cs, /ras, /cas = low, /we, cke = high) this command is a request to begin the cbr (auto) refresh operation. the refresh address is generated internally. before executing cbr (auto) refresh, all banks must be precharged. after this cycle, all banks will be in the idle (precharged) state and ready for a row activate command. during t rc period (from refresh command to refresh or activate command), the pd45128xxx cannot accept any other command. fig.6 cbr (auto) refresh command add a10 ba0(a13), ba1(a12) /we /cas /ras /cs cke clk h data sheet e0031n30 13 pd45128441, 45128841, 45128163 self refresh entry command (/cs, /ras, /cas, cke = low, /we = high) after the command execution, self refresh operation continues while cke remains low. when cke goes high, the pd45128xxx exits the self refresh mode. during self refresh mode, refresh interval and refresh operation are performed internally, so there is no need for external control. before executing self refresh, all banks must be precharged. fig.7 self refresh entry command /we /cas /ras /cs cke clk add a10 ba0(a13), ba1(a12) burst stop command (/cs, /we = low, /ras, /cas = high) this command can stop the current burst operation. fig.8 burst stop command in full page mode /we /cas /ras /cs cke clk add a10 ba0(a13), ba1(a12) h no operation (/cs = low, /ras, /cas, /we = high) this command is not an execution command. no operations begin or terminate by this command. fig.9 no operation /we /cas /ras /cs cke clk h add a10 ba0(a13), ba1(a12) data sheet e0031n30 14 pd45128441, 45128841, 45128163 3. simplified state diagram cke cke cke cke cke cke cke cke precharge auto precharge pre read with auto precharge read bst bst pre (precharge termination) pre (precharge termination) act mrs ref cke cke self self exit idle mode register set cbr (auto) refresh row active self refresh power down active power down precharge read reada read suspend reada suspend write writea write suspend writea suspend power on write read automatic sequence manual input cke cke read write write with write data sheet e0031n30 15 pd45128441, 45128841, 45128163 4. truth table 4.1 command truth table function symbol cke /cs /ras /cas /we ba1, a10 a11, n ? 1 n ba0 a9 - a0 device deselect desl h h no operation nop h l h h h burst stop bst h l h h l read read h l h l h v l v read with auto precharge reada h l h l h v h v write writ h l h l l v l v write with auto precharge writa h l h l l v h v bank activate act h l l h h v v v precharge select bank pre h l l h l v l precharge all banks pall h l l h l h mode register set mrs h l l l l l l v remark h = high level, l = low level, = high or low level (don't care), v = valid data input 4.2 dqm truth table function symbol cke dqm n ? 1 n u l data write / output enable enb h l data mask / output disable mask h h upper byte write enable / output enable enbu h l lower byte write enable / output enable enbl h l upper byte write inhibit / output disable masku h h lower byte write inhibit / output disable maskl h h remark h = high level, l = low level, = high or low level (don't care) 4.3 cke truth table current state function symbol cke /cs /ras /cas /we address n ? 1 n activating clock suspend mode entry h l any clock suspend mode l l clock suspend clock suspend mode exit l h idle cbr (auto) refresh command ref h h l l l h idle self refresh entry self h l l l l h self refresh self refresh exit l h l h h h l h h idle power down entry h l power down power down exit l h h l h l h h h remark h = high level, l = low level, = high or low level (don't care) data sheet e0031n30 16 pd45128441, 45128841, 45128163 4.4 operative command table note1 (1/3) current state /cs /ras /cas /we address command action notes idle h desl nop or power down 2 l h h nop or bst nop or power down 2 l h l h ba, ca, a10 read/reada illegal 3 l h l l ba, ca, a10 writ/writa illegal 3 l l h h ba, ra act row activating l l h l ba, a10 pre/pall nop l l l h ref/self cbr (auto) refresh or self refresh 4 l l l l op-code mrs mode register accessing row active h desl nop l h h nop or bst nop l h l h ba, ca, a10 read/reada begin read : determine ap 5 l h l l ba, ca, a10 writ/writa begin write : determine ap 5 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/pall precharge 6 l l l h ref/self illegal l l l l op-code mrs illegal read h desl continue burst to end row active l h h h nop continue burst to end row active l h h l bst burst stop row active l h l h ba, ca, a10 read/reada terminate burst, new read : determine ap 7 l h l l ba, ca, a10 writ/writa terminate burst, start write : determine ap 7, 8 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/pall terminate burst, precharging l l l h ref/self illegal l l l l op-code mrs illegal write h desl continue burst to end write recovering l h h h nop continue burst to end write recovering l h h l bst burst stop row active l h l h ba, ca, a10 read/reada terminate burst, start read : determine ap 7, 8 l h l l ba, ca, a10 writ/writa terminate burst, new write : determine ap 7 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/pall terminate burst, precharging 9 l l l h ref/self illegal l l l l op-code mrs illegal data sheet e0031n30 17 pd45128441, 45128841, 45128163 (2/3) current state /cs /ras /cas /we address command action notes read with auto h desl continue burst to end precharging precharge l h h h nop continue burst to end precharging l h h l bst illegal l h l h ba, ca, a10 read/reada illegal 3 l h l l ba, ca, a10 writ/writa illegal 3 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/pall illegal 3 l l l h ref/self illegal l l l l op-code mrs illegal write with auto precharge h desl continue burst to end write recovering with auto precharge l h h h nop continue burst to end write recovering with auto precharge l h h l bst illegal l h l h ba, ca, a10 read/reada illegal 3 l h l l ba, ca, a10 writ/writa illegal 3 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/pall illegal 3 l l l h ref/self illegal l l l l op-code mrs illegal precharging h desl nop enter idle after t rp l h h h nop nop enter idle after t rp l h h l bst illegal l h l h ba, ca, a10 read/reada illegal 3 l h l l ba, ca, a10 writ/writa illegal 3 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/pall nop enter idle after t rp l l l h ref/self illegal l l l l op-code mrs illegal row activating h desl nop enter bank active after t rcd l h h h nop nop enter bank active after t rcd l h h l bst illegal l h l h ba, ca, a10 read/reada illegal 3 l h l l ba, ca, a10 writ/writa illegal 3 l l h h ba, ra act illegal 3, 10 l l h l ba, a10 pre/pall illegal 3 l l l h ref/self illegal l l l l op-code mrs illegal data sheet e0031n30 18 pd45128441, 45128841, 45128163 (3/3) current state /cs /ras /cas /we address command action notes write recovering h desl nop enter row active after t dpl l h h h nop nop enter row active after t dpl l h h l bst nop enter row active after t dpl l h l h ba, ca, a10 read/reada start read, determine ap 8 l h l l ba, ca, a10 writ/writa new write, determine ap l l h h ba, ra act illegal 3 l l h l ba, a10 pre/pall illegal 3 l l l h ref/self illegal l l l l op-code mrs illegal write recovering h desl nop enter precharge after t dpl with auto precharge l h h h nop nop enter precharge after t dpl l h h l bst nop enter precharge after t dpl l h l h ba, ca, a10 read/reada illegal 3, 8 l h l l ba, ca, a10 writ/writa illegal 3 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/pall illegal l l l h ref/self illegal l l l l op-code mrs illegal refreshing h desl nop enter idle after t rc l h h nop/bst nop enter idle after t rc l h l read/writ illegal l l h act/pre/pall illegal l l l ref/self/mrs illegal mode register h desl nop enter idle after t rsc accessing l h h h nop nop enter idle after t rsc l h h l bst illegal l h l read/writ illegal l l act/pre/pall/ ref/self/mrs illegal notes 1. all entries assume that cke was active (high level) during the preceding clock cycle. 2. if all banks are idle, and cke is inactive (low level), pd45128xxx will enter power down mode. all input buffers except cke will be disabled. 3. illegal to bank in specified states; function may be legal in the bank indicated by bank address (ba), depending on the state of that bank. 4. if all banks are idle, and cke is inactive (low level), pd45128xxx will enter self refresh mode. all input buffers except cke will be disabled. 5. illegal if t rcd is not satisfied. 6. illegal if t ras is not satisfied. 7. must satisfy burst interrupt condition. 8. must satisfy bus contention, bus turn around, and/or write recovery requirements. 9. must mask preceding data which don't satisfy t dpl . 10. illegal if t rrd is not satisfied. remark h = high level, l = low level, = high or low level (don?t care), v = valid data data sheet e0031n30 19 pd45128441, 45128841, 45128163 4.5 command truth table for cke current state cke /cs /ras /cas /we address action notes n ? 1 n self refresh h invalid, clk (n ? 1) would exit self refresh l h h self refresh recovery l h l h h self refresh recovery l h l h l illegal l h l l illegal l l maintain self refresh self refresh recovery h h h idle after t rc h h l h h idle after t rc h h l h l illegal h h l l illegal h l h illegal h l l h h illegal h l l h l illegal h l l l illegal power down h invalid, clk (n ? 1) would exit power down l h h exit power down idle l h l h h h exit power down idle l l maintain power down mode all banks idle h h h refer to operations in operative command table h h l h refer to operations in operative command table h h l l h refer to operations in operative command table h h l l l h cbr (auto) refresh h h l l l l op-code refer to operations in operative command table h l h refer to operations in operative command table h l l h refer to operations in operative command table h l l l h refer to operations in operative command table h l l l l h self refresh 1 h l l l l l op-code refer to operations in operative command table l power down 1 row active h refer to operations in operative command table l power down 1 any state other than h h refer to operations in operative command table listed above h l begin clock suspend next cycle 2 l h exit clock suspend next cycle l l maintain clock suspend notes 1. self refresh can be entered only from the all banks idle state. power down can be entered only from all banks idle or row active state. 2. must be legal command as defined in operative command table. remark h = high level, l = low level, = high or low level (don't care) data sheet e0031n30 20 pd45128441, 45128841, 45128163 5. initialization the synchronous dram is initialized in the power-on sequence according to the following. (1) to stabilize internal circuits, when power is applied, a 100 s or longer pause must precede any signal toggling. (2) after the pause, all banks must be precharged using the precharge command (the precharge all banks command is convenient). (3) once the precharge is completed and the minimum t rp is satisfied, the mode register can be programmed. after the mode register set cycle, t rsc (2 clk minimum) pause must be satisfied as well. (4) two or more cbr (auto) refresh must be performed. remarks 1. the sequence of mode register programming and refresh above may be transposed. 2. cke and dqm must be held high until the precharge command is issued to ensure data-bus hi-z. data sheet e0031n30 21 pd45128441, 45128841, 45128163 6. programming the mode register the mode register is programmed by the mode register set command using address bits a11 through a0, ba0(a13) and ba1(a12) as data inputs. the register retains data until it is reprogrammed or the device loses power. the mode register has four fields; options : a11 through a7, ba0(a13), ba1(a12) /cas latency : a6 through a4 wrap type : a3 burst length : a2 through a0 following mode register programming, no command can be issued before at least 2 clk have elapsed. /cas latency /cas latency is the most critical of the parameters being set. it tells the device how many clocks must elapse before the data will be available. the value is determined by the frequency of the clock and the speed grade of the device. 13.3 relationship between frequency and latency shows the relationship of /cas latency to the clock period and the speed grade of the device. burst length burst length is the number of words that will be output or input in a read or write cycle. after a read burst is completed, the output bus will become hi-z. the burst length is programmable as 1, 2, 4, 8 or full page. wrap type (burst sequence) the wrap type specifies the order in which the burst data will be addressed. this order is programmable as either ?sequential? or ?interleave?. the method chosen will depend on the type of cpu in the system. some microprocessor cache systems are optimized for sequential addressing and others for interleaved addressing. 7.1 burst length and sequence shows the addressing sequence for each burst length using them. both sequences support bursts of 1, 2, 4 and 8. additionally, sequence supports the full page length. data sheet e0031n30 22 pd45128441, 45128841, 45128163 7. mode register wt = 1 1 2 4 8 r r r r 1 0 0 0 0 jedec standard test set (refresh counter test) bl wt ltmode 0 0 1 x x burst read and single write (for write through cache) 0 1 use in future v v v v v v 1v 1 x x x vender specific bl wt ltmode 0 0 0 0 0 mode register set v = valid x = don?t care wt = 0 1 2 4 8 r r r full page bits2-0 000 001 010 011 100 101 110 111 burst length sequential interleave 0 1 wrap type /cas latency r r 2 3 r r r r bits6-4 000 001 010 011 100 101 110 111 latency mode 0 0 a0 a1 a2 a3 a4 a5 a7 a6 a8 a9 a10 a11 ba1 (a12) ba0 (a13) a0 a1 a2 a3 a4 a5 a7 a6 a8 a9 a10 a11 ba1 (a12) ba0 (a13) a0 a1 a2 a3 a4 a5 a7 a6 a8 a9 a10 a11 ba1 (a12) ba0 (a13) a0 a1 a2 a3 a4 a5 a7 a6 a8 a9 a10 a11 ba1 (a12) ba0 (a13) a0 a1 a2 a3 a4 a5 a7 a6 a8 a9 a10 a11 ba1 (a12) ba0 (a13) x x x x 0 0 remark r : reserved clk cke /cs /ras /cas /we a0 - a11, ba0(13), ba1(a12) mode register set mode register set timing data sheet e0031n30 23 pd45128441, 45128841, 45128163 7.1 burst length and sequence [burst of two] starting address (column address a0, binary) sequential addressing sequence (decimal) interleave addressing sequence (decimal) 0 0, 1 0, 1 1 1, 0 1, 0 [burst of four] starting address (column address a1 - a0, binary) sequential addressing sequence (decimal) interleave addressing sequence (decimal) 00 0, 1, 2, 3 0, 1, 2, 3 01 1, 2, 3, 0 1, 0, 3, 2 10 2, 3, 0, 1 2, 3, 0, 1 11 3, 0, 1, 2 3, 2, 1, 0 [burst of eight] starting address (column address a2 - a0, binary) sequential addressing sequence (decimal) interleave addressing sequence (decimal) 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 full page burst is an extension of the above tables of sequential addressing, with the length being 2,048 (for 32m 4 device), 1,024 (for 16m 8 device), and 512 (for 8m 16 device). data sheet e0031n30 24 pd45128441, 45128841, 45128163 8. address bits of bank-select and precharge a11 a10 a9 a8 a7 a6 a4 a5 a3 a2 a1 a0 row (activate command) a11 a10 a9 a8 a7 a6 a4 a5 a3 a2 a1 a0 (precharge command) disables auto-precharge (end of burst) 0 enables auto-precharge (end of burst) 1 x a10 a9 a8 a7 a6 a4 a5 a3 a2 a1 a0 col. (/cas strobes) x : don ? t care select bank a ?activate? command 0 select bank b ?activate? command 0 1 1 0 1 0 1 ba1(a12) ba0(a13) ba1(a12) ba0(a13) ba1(a12) ba0(a13) result select bank c ?activate? command select bank d ?activate? command enables read/write commands for bank a 0 enables read/write commands for bank b 0 1 1 0 1 0 1 result enables read/write commands for bank c enables read/write commands for bank d result precharge bank a precharge bank b precharge bank c precharge bank d precharge all banks a10 0 0 0 0 1 0 0 1 1 x 0 1 0 1 x ba1 (a12) ba0 (a13) ba1 (a12) ba0 (a13) ba1 (a12) ba0 (a13) data sheet e0031n30 25 pd45128441, 45128841, 45128163 9. precharge the precharge command can be issued anytime after t ras (min.) is satisfied. soon after the precharge command is issued, precharge operation performed and the synchronous dram enters the idle state after t rp is satisfied. the parameter t rp is the time required to perform the precharge. the earliest timing in a read cycle that a precharge command can be issued without losing any data in the burst is as follows. it is depending on the /cas latency and clock cycle time. t0 t1 t2 t3 t4 t5 t6 t7 burst length=4 read read q1 q2 q3 q4 pre hi-z q1 q2 q3 q4 pre hi-z (t ras must be satisfied) clk command /cas latency = 2 dq command /cas latency = 3 dq t8 in order to write all data to the memory cell correctly, the asynchronous parameter ?t dpl ? must be satisfied. the t dpl (min.) specification defines the earliest time that a precharge command can be issued. minimum number of clocks is calculated by dividing t dpl (min.) with clock cycle time. in summary, the precharge command can be issued relative to reference clock that indicates the last data word is valid. in the following table, minus means clocks before the reference; plus means time after the reference. /cas latency read write 2 ?1 +t dpl (min.) 3 ?2 +t dpl (min.) data sheet e0031n30 26 pd45128441, 45128841, 45128163 10. auto precharge during a read or write command cycle, a10 controls whether auto precharge is selected. a10 high in the read or write command (read with auto precharge command or write with auto precharge command), auto precharge is selected and begins automatically. the t ras must be satisfied with a read with auto precharge or a write with auto precharge operation. in addition, the next activate command to the bank being precharged cannot be executed until the precharge cycle ends. in read cycle, once auto precharge has started, an activate command to the bank can be issued after t rp has been satisfied. in write cycle, the t dal must be satisfied to issue the next activate command to the bank being precharged. the timing that begins the auto precharge cycle depends on both the /cas latency programmed into the mode register and whether read or write cycle. 10.1 read with auto precharge during a read cycle, the auto precharge begins one clock earlier (/cas latency of 2) or two clocks earlier (/cas latency of 3) the last data word output. qb1 qb2 qb3 qb4 auto precharge starts reada b hi-z qb1 qb2 qb3 qb4 auto precharge starts reada b hi-z dq command dq command /cas latency = 2 /cas latency = 3 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 burst length = 4 (t ras must be satisfied) t9 remark reada means read with auto precharge data sheet e0031n30 27 pd45128441, 45128841, 45128163 10.2 write with auto precharge during a write cycle, the auto precharge starts at the timing that is equal to the value of the t dpl (min.) after the last data word input to the device. db1 db2 db3 db4 auto precharge starts writa b hi-z db1 db2 db3 db4 auto precharge starts writa b hi-z dq command dq command /cas latency = 2 /cas latency = 3 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 burst length = 4 (t ras must be satisfied) t dpl(min.) t dpl(min.) remark writa means write with auto precharge in summary, the auto precharge begins relative to a reference clock that indicates the last data word is valid. in the table below, minus means clocks before the reference; plus means after the reference. /cas latency read write 2 ?1 +t dpl (min.) 3 ?2 +t dpl (min.) data sheet e0031n30 28 pd45128441, 45128841, 45128163 11. read / write command interval 11.1 read to read command interval during a read cycle, when new read command is issued, it will be effective after /cas latency, even if the previous read operation does not completed. read will be interrupted by another read. the interval between the commands is 1 cycle minimum. each read command can be issued in every clock without any restriction. qb1 qb2 qb3 qb4 hi-z read a dq command clk t0 t2 t1 t3 t4 t5 t6 t7 t8 burst length = 4, /cas latency = 2 read b qa1 1cycle t9 11.2 write to write command interval during a write cycle, when a new write command is issued, the previous burst will terminate and the new burst will begin with a new write command. write will be interrupted by another write. the interval between the commands is minimum 1 cycle. each write command can be issued in every clock without any restriction. db1 db2 db3 db4 hi-z write a dq command clk t0 t2 t1 t3 t4 t5 t6 t7 t8 burst length = 4, /cas latency = 2 write b da1 1cycle data sheet e0031n30 29 pd45128441, 45128841, 45128163 11.3 write to read command interval write command and read command interval is also 1 cycle. only the write data before read command will be written. the data bus must be hi-z at least one cycle prior to the first d out . qb1 qb2 qb3 qb4 write a hi-z qb1 qb2 qb3 qb4 write a hi-z dq command dq command /cas latency = 2 /cas latency = 3 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 burst length = 4 da1 da1 read b read b data sheet e0031n30 30 pd45128441, 45128841, 45128163 11.4 read to write command interval during a read cycle, read can be interrupted by write. the read and write command interval is 1 cycle minimum. there is a restriction to avoid data conflict. the data bus must be hi-z using dqm before write. d1 d2 d3 d4 read dq command clk t0 t2 t1 t3 t4 t5 t6 t7 t8 burst length = 4 write dqm hi-z 1cycle read can be interrupted by write. dqm must be high at least 3 clocks prior to the write command. clk t0 t2 t1 t3 t4 t5 t6 t7 t8 burst length = 8 t9 q1 q2 q3 read dq command d1 d2 d3 write dqm hi-z is necessary q1 q2 read dq command d1 d2 d3 write dqm hi-z is necessary /cas latency = 2 /cas latency = 3 data sheet e0031n30 31 pd45128441, 45128841, 45128163 12. burst termination there are two methods to terminate a burst operation other than using a read or a write command. one is the burst stop command and the other is the precharge command. 12.1 burst stop command during a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus goes to hi-z after the /cas latency from the burst stop command. read command clk t0 t2 t1 t3 t4 t5 t6 t7 burst length = x q1 q2 q3 dq /cas latency = 2 hi-z q1 q2 q3 dq /cas latency = 3 hi-z bst remark bst: burst stop command during a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes to hi-z at the same clock with the burst stop command. d2 d3 d4 write dq command /cas latency = 2, 3 clk t0 t2 t1 t3 t4 t5 t6 t7 burst length = x bst hi-z d1 remark bst: burst stop command data sheet e0031n30 32 pd45128441, 45128841, 45128163 12.2 precharge termination 12.2.1 precharge termination in read cycle during a read cycle, the burst read operation is terminated by a precharge command. when the precharge command is issued, the burst read operation is terminated and precharge starts. the same bank can be activated again after t rp from the precharge command. to issue a precharge command, t ras must be satisfied. when /cas latency is 2, the read data will remain valid until one clock after the precharge command. read clk t0 t2 t1 t3 t4 t5 t6 t7 burst length = x, /cas latency = 2 q1 dq command q2 q3 q4 act t rp pre hi-z (t ras must be satisfied) when /cas latency is 3, the read data will remain valid until two clocks after the precharge command. read clk t0 t2 t1 t3 t4 t5 t6 t7 burst length = x, /cas latency = 3 dq command q1 q2 q3 act t rp pre hi-z t8 q4 (t ras must be satisfied) data sheet e0031n30 33 pd45128441, 45128841, 45128163 12.2.2 precharge termination in write cycle during a write cycle, the burst write operation is terminated by a precharge command. when the precharge command is issued, the burst write operation is terminated and precharge starts. the same bank can be activated again after t rp from the precharge command. to issue a precharge command, t ras must be satisfied. when /cas latency is 2, the write data written prior to the precharge command will be correctly stored. however, invalid data may be written at the same clock as the precharge command. to prevent this from happening, dqm must be high at the same clock as the precharge command. this will mask the invalid data. write clk t0 t2 t1 t3 t4 t5 t6 t7 burst length = x, /cas latency = 2 dq command d1 d2 d3 act dqm t rp pre hi-z d4 d5 (t ras must be satisfied) when /cas latency is 3, the write data written prior to the precharge command will be correctly stored. however, invalid data may be written at the same clock as the precharge command. to prevent this from happening, dqm must be high at the same clock as the precharge command. this will mask the invalid data. write clk t0 t2 t1 t3 t4 t5 t6 t7 burst length = x, /cas latency = 3 dq command d1 d2 d3 act dqm t rp pre hi-z d5 t8 d4 (t ras must be satisfied) data sheet e0031n30 34 pd45128441, 45128841, 45128163 13. electrical specifications ? all voltages are referenced to v ss (gnd). ? after power up, wait more than 100 s and then, execute power on sequence and cbr (auto) refresh before proper device operation is achieved. absolute maximum ratings parameter symbol condition rating unit voltage on power supply pin relative to gnd v cc , v cc q ? 0.5 to +4.6 v voltage on any pin relative to gnd v t ? 0.5 to +4.6 v short circuit output current i o 50 ma power dissipation p d 1 w operating ambient temperature t a 0 to 70 c storage temperature t stg ? 55 to + 125 c caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol condition min. typ. max. unit supply voltage v cc , v cc q 3.0 3.3 3.6 v high level input voltage v ih 2.0 v cc +0.3 note1 v low level input voltage v il ? 0.3 note2 +0.8 v operating ambient temperature t a 0 70 c notes 1. v ih (max.) = v cc + 1.5 v (pulse width 5 ns) 2. v il (min.) = ?1.5 v (pulse width 5 ns) pin capacitance (t a = 25 c, f = 1 mhz) parameter symbol condition min. typ. max. unit input capacitance c i1 clk 2.5 3.5 pf c i2 a0 - a11, ba0(a13), ba1(a12), cke, /cs, /ras, /cas, /we, dqm, udqm, ldqm 2.5 3.8 data input / output capacitance c i/o dq0 - dq15 4 6.5 pf data sheet e0031n30 35 pd45128441, 45128841, 45128163 dc characteristics 1 (recommended operating conditions unless otherwise noted) parameter symbol test condition /cas grade maximum unit notes latency 4 8 16 operating current i cc1 burst length = 1, cl = 2 -a75a 110 110 120 ma 1 t rc t rc (min.) , io = 0 ma, -a75 100 100 110 one bank active -a80 100 100 110 -a10 100 100 110 cl = 3 -a75a 110 110 120 -a75 105 105 115 -a80 100 100 110 -a10 100 100 110 precharge standby current i cc2 p cke v il (max.) , t ck = 15 ns 1 1 1 ma in power down mode i cc2 ps cke v il (max.) , t ck = 1 1 1 precharge standby current in non power down mode i cc2 n cke v ih (min.) , t ck = 15 ns, /cs v ih (min.) , input signals are changed one time during 30 ns. 20 20 20 ma i cc2 ns cke v ih (min.) , t ck = , input signals are stable. 8 8 8 active standby current i cc3 p cke v il (max.) , t ck = 15 ns 5 5 5 ma in power down mode i cc3 ps cke v il (max.) , t ck = 4 4 4 active standby current in non power down mode i cc3 n cke v ih (min.) , t ck = 15 ns, /cs v ih (min.) , input signals are changed one time during 30 ns. 30 30 30 ma i cc3 ns cke v ih (min.) , t ck = , input signals are stable. 20 20 20 operating current i cc4 t ck t ck (min.) , io = 0 ma, cl = 2 -a75a 140 155 185 ma 2 (burst mode) all banks active -a75 105 120 145 -a80 105 120 145 -a10 85 95 110 cl = 3 -a75a 140 155 185 -a75 140 155 185 -a80 130 145 175 -a10 110 125 140 cbr (auto) refresh current i cc5 t rc t rc (min.) cl = 2 -a75a 270 270 270 ma 3 -a75 230 230 230 -a80 230 230 230 -a10 230 230 230 cl = 3 -a75a 270 270 270 -a75 240 240 240 -a80 230 230 230 -a10 230 230 230 self refresh current i cc6 cke 0.2 v -** 2 2 2 ma -**l 0.8 0.8 0.8 ma notes 1. i cc1 depends on output loading and cycle rates. specified values are obtained with the output open. in addition to this, i cc1 is measured condition that addresses are changed only one time during t ck (min.) . 2. i cc4 depends on output loading and cycle rates. specified values are obtained with the output open. in addition to this, i cc4 is measured condition that addresses are changed only one time during t ck (min.) . 3. i cc5 is measured on condition that addresses are changed only one time during t ck (min.) . data sheet e0031n30 36 pd45128441, 45128841, 45128163 dc characteristics 2 (recommended operating conditions unless otherwise noted) parameter symbol test condition min. typ. max. unit note input leakage current i i (l) 0 v i v cc q, v cc q = v cc all other pins not under test = 0 v ? 1.0 +1.0 a output leakage current i o (l) 0 v o v cc q, d out is disabled ? 1.5 +1.5 a high level output voltage v oh i o = ? 4 ma 2.4 v low level output voltage v ol i o = +4 ma 0.4 v ac characteristics (recommended operating conditions unless otherwise noted) test conditions parameter value unit ac high level input voltage / low level input voltage 2.4 / 0.4 v input timing measurement reference level 1.4 v transition time (input rise and fall time) 1 ns output timing measurement reference level 1.4 v t ck t ch t cl 2.4 v 1.4 v 0.4 v clk 2.4 v 1.4 v 0.4 v input t setup t hold output t ac t oh data sheet e0031n30 37 pd45128441, 45128841, 45128163 synchronous characteristics parameter symbol -a75a -a75 -a80 -a10 unit note min. max. min. max. min. max. min. max. clock cycle time /cas latency = 3 t ck3 7.5 (133 mhz) 7.5 (133 mhz) 8 ( 125 mhz ) 10 ( 100 mhz ) ns /cas latency = 2 t ck2 7.5 (133 mhz) 10 (100 mhz) 10 ( 100 mhz ) 13 (77 mhz) ns access time from clk /cas latency = 3 t ac3 5.4 5.4 6 6 ns 1 /cas latency = 2 t ac2 5.4 6 6 7 ns 1 clk high level width t ch 2.5 2.5 3 3 ns clk low level width t cl 2.5 2.5 3 3 ns data-out hold time t oh 3 3 3 3 ns 1 data-out low-impedance time t lz 0 0 0 0 ns data-out high-impedance time /cas latency = 3 t hz3 3 5.4 3 5.4 3 6 3 6 ns /cas latency = 2 t hz2 3 5.4 3 6 3 6 3 7 ns data-in setup time t ds 1.5 1.5 2 2 ns data-in hold time t dh 0.8 0.8 1 1 ns address setup time t as 1.5 1.5 2 2 ns address hold time t ah 0.8 0.8 1 1 ns cke setup time t cks 1.5 1.5 2 2 ns cke hold time t ckh 0.8 0.8 1 1 ns cke setup time (power down exit) t cksp 1.5 1.5 2 2 ns command (/cs, /ras, /cas, /we, dqm) setup time t cms 1.5 1.5 2 2 ns command (/cs, /ras, /cas, /we, dqm) hold time t cmh 0.8 0.8 1 1 ns note 1. output load output z = 50 ? 50 pf data sheet e0031n30 38 pd45128441, 45128841, 45128163 asynchronous characteristics parameter symbol -a75a -a 75 -a80 -a 10 unit note min. max. min. max. min. max. min. max. act to ref/act command period (operation) t rc 60 67.5 70 70 ns ref to ref/act command period (refresh) t rc1 60 67.5 70 70 ns act to pre command period t ras 45 120,000 45 120,000 48 120,000 50 120,000 ns pre to act command period t rp 15 20 20 20 ns delay time act to read/write command t rcd 15 20 20 20 ns act (one) to act (another) command period t rrd 15 15 16 20 ns data-in to pre command period t dpl 8 8 8 10 ns data-in to act (ref) command period /cas latency = 3 t dal3 1clk +22.5 1clk +22.5 1clk +20 1clk +20 ns 1 (auto precharge) /cas latency = 2 t dal2 1clk +20 1clk +20 1clk +20 1clk +20 ns mode register set cycle time t rsc 2 2 2 2 clk transition time t t 0.5 30 0.5 30 0.5 30 1 30 ns refresh time (4,096 refresh cycles) t ref 64 64 64 64 ms note 1. the ?a75a and ?a75 grade device can satisfy the t dal3 spec of 1clk+20 ns for up to and including 125mhz operation. data sheet e0031n30 39 pd45128441, 45128841, 45128163 13.1 ac parameters for read timing (manual precharge, burst length = 4, /cas latency = 3) t oh t lz t ac t oh t ac t ac t oh t oh t ac t hz t ras t rc ba0 t ckh t rp t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 clk cke /cs /ras /cas /we ba1 a10 add dqm dq t rcd t cks t ch t cl t ck t cms t cmh t as t ah l hi-z activate command for bank a precharge command for bank a read command for bank a activate command for bank a data sheet e0031n30 40 pd45128441, 45128841, 45128163 t cks ac parameters for read timing (auto precharge, burst length = 4, /cas latency = 3) t oh t lz t ac t oh t ac t ac t oh t oh t ac t hz t ras t rrd t rc ba0 t ckh t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 clk cke /cs /ras /cas /we ba1 a10 add dqm dq t rcd t ch t cl t ck t cms t cmh t as t ah l hi-z auto precharge start for bank c activate command for bank c activate command for bank d read with auto precharge command for bank c activate command for bank c data sheet e0031n30 41 pd45128441, 45128841, 45128163 13.2 ac parameters for write timing (burst length = 4, /cas latency = 3) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke ba0 a10 add dqm dq hi-z t as t ah t ds t dh t rcd t dal t rc t rrd t rcd t ras t rc t dpl t rp t ckh t cms t cmh t cks /cs /ras /cas /we ba1 auto precharge start for bank c l activate command for bank c activate command for bank b write command for bank b activate command for bank b write with auto precharge command for bank c precharge command for bank b activate command for bank c data sheet e0031n30 42 pd45128441, 45128841, 45128163 13.3 relationship between frequency and latency speed version -75a -75 -80 -10 clock cycle time [ns] 7.5 7.5 7.5 10 8 10 10 13 frequency [mhz] 133 133 133 100 125 100 100 77 /cas latency 3 2 3 2 3 2 3 2 [t rcd ] 2 2 3 2 3 2 2 2 /ras latency (/cas latency + [t rcd ]) 5 4 6 4 6 4 5 4 [t rc ] 8 8 9 7 9 7 7 6 [t rc1 ] 8 8 9 7 9 7 8 6 [t ras ] 6 6 6 5 6 5 5 4 [t rrd ] 2 2 2 2 2 2 2 2 [t rp ] 2 2 3 2 3 2 2 2 [t dpl ] 2 2 2 1 1 1 1 1 [t dal ] 4 4 4 3 4 3 3 3 [t rsc ] 2 2 2 2 2 2 2 2 data sheet e0031n30 43 pd45128441, 45128841, 45128163 13.4 mode register set (burst length = 4, /cas latency = 2) clk cke /cs /ras /cas /we ba0 a10 add dqm dq ba1 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 hi-z address key t rp precharge all banks command mode register set command activate command is valid h t rsc 2 clk (min.) data sheet e0031n30 44 pd45128441, 45128841, 45128163 13.5 power on sequence and cbr (auto) refresh clk cke /cs /ras /cas /we ba1 a10 add dqm dq hi-z t rsc address key t rp high level is necessary 2 refresh cycles are necessary t rc1 t rc1 precharge all banks command is necessary mode register set command is necessary cbr (auto) refresh command is necessary activate command cbr (auto) refresh command is necessary ba0 high level is necessary clock cycle is necessary data sheet e0031n30 45 pd45128441, 45128841, 45128163 13.6 /cs function (burst length = 4, /cas latency = 3) only /cs signal needs to be issued at minimum rate clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 h l hi-z l ba0 l raa qaa1 qaa2 qaa3 qaa4 dab1 dab2 dab3 dab4 activate command for bank a read command for bank a write command for bank a precharge command for bank a raa caa cab data sheet e0031n30 46 pd45128441, 45128841, 45128163 13.7 clock suspension during burst read (using cke function) (1/2) (burst length = 4, /cas latency = 2) clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 qaa1 qaa2 qaa3 qaa4 caa ba0 l hi-z raa raa activate command for bank a read command for bank a 1-clock suspended 2-clock suspended 3-clock suspended hi-z (turn off) at the end of burst data sheet e0031n30 47 pd45128441, 45128841, 45128163 clock suspension during burst read (using cke function) (2/2) (burst length = 4, /cas latency = 3) clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 qaa1 qaa2 qaa3 qaa4 caa ba0 l hi-z raa raa activate command for bank a read command for bank a 1-clock suspended 2-clock suspended 3-clock suspended hi-z (turn off) at the end of burst data sheet e0031n30 48 pd45128441, 45128841, 45128163 13.8 clock suspension during burst write (using cke function) (1/2) (burst length = 4, /cas latency = 2) clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 caa ba0 l hi-z raa raa daa1 daa2 daa3 daa4 activate command for bank a 1-clock suspended 2-clock suspended 3-clock suspended write command for bank a data sheet e0031n30 49 pd45128441, 45128841, 45128163 clock suspension during burst write (using cke function) (2/2) (burst length = 4, /cas latency = 3) clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 caa ba0 l hi-z raa raa daa1 daa2 daa3 daa4 activate command for bank a 1-clock suspended 2-clock suspended 3-clock suspended write command for bank a data sheet e0031n30 50 pd45128441, 45128841, 45128163 13.9 power down mode and clock mask (burst length = 4, /cas latency = 2) clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 qaa3 caa l hi-z raa ba0 t cksp t cksp qaa1 qaa2 valid activate command for bank a power down mode entry active standby power down mode exit read command for bank a clock mask start clock mask end power down mode entry precharge command for bank a precharge standby power down mode exit qaa4 raa data sheet e0031n30 51 pd45128441, 45128841, 45128163 13.10 cbr (auto) refresh clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 tn tn + 1tn + 2tn + 3tn + 4tn + 5tn + 6tmtm + 1tm + 2tm + 3tm + 4tm + 5tm + 6tm + 7 ba0 l hi-z t rp h t rc1 t rc1 q1 precharge command (if necessary) cbr (auto) refresh cbr (auto) refresh activate command read command data sheet e0031n30 52 pd45128441, 45128841, 45128163 13.11 self refresh (entry and exit) clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 tn tn + 1tn + 2tmtm + 1tktk + 1tk + 2tk + 3tk + 4 t rp t rc1 t rc1 ba0 precharge command (if necessary) self refresh entry self refresh exit next clock enable self refresh entry (or activate command) activate command self refresh exit next clock enable l hi-z data sheet e0031n30 53 pd45128441, 45128841, 45128163 13.12 random column read (page with same bank) (1/2) (burst length = 4, /cas latency = 2) clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 qaa1 qaa2 qaa3 qaa4 qab1 qab2 qac1 qac2 qac3 qac4 qad1 qad2 qad3 h rad raa cad cac caa rad cab ba0 raa precharge command for bank a activate command for bank a read command for bank a read command for bank a read command for bank a activate command for bank a read command for bank a l hi-z data sheet e0031n30 54 pd45128441, 45128841, 45128163 random column read (page with same bank) (2/2) (burst length = 4, /cas latency = 3) clk cke /cs /ras /cas /we ba1 a10 add dqm dq precharge command for bank a activate command for bank a read command for bank a read command for bank a read command for bank a activate command for bank a read command for bank a t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 qaa1 qaa2 qaa3 qaa4 qab1 qab2 qac1 qac2 qac3 qac4 h raa raa caa cac caa raa cab ba0 raa l hi-z data sheet e0031n30 55 pd45128441, 45128841, 45128163 13.13 random column write (page with same bank) (1/2) (burst length = 4, /cas latency = 2) clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l hi-z dda1 dda2 dda3 dda4 ddb1 ddb2 ddc1 ddc2 ddc3 ddc4 ddd1 ddd2 ddd3 h rdd rda cdd cdc cda rdd cdb ba0 rda ddd4 activate command for bank d write command for bank d write command for bank d write command for bank d precharge command for bank d activate command for bank d write command for bank d data sheet e0031n30 56 pd45128441, 45128841, 45128163 random column write (page with same bank) (2/2) (burst length = 4, /cas latency = 3) clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l hi-z dda1 dda2 dda3 dda4 ddb1 ddb2 ddc1 ddc2 ddc3 ddc4 h rdd rda cdd cdc cda rdd cdb ba0 rda ddd1 activate command for bank d write command for bank d write command for bank d write command for bank d precharge command for bank d activate command for bank d write command for bank d ddd2 data sheet e0031n30 57 pd45128441, 45128841, 45128163 13.14 random row read (ping-pong banks) (1/2) (burst length = 8, /cas latency = 2) clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l hi-z qda1 qda2 qda3 qda4 qda5 qda6 qda7 qda8 qba1 qba2 qba3 qba4 qba5 h rdb rda cdb cba cda rdb rba rda ba0 rba qba6 qba7 qba8 activate command for bank d read command for bank d activate command for bank b read command for bank b precharge command for bank d activate command for bank d read command for bank d data sheet e0031n30 58 pd45128441, 45128841, 45128163 random row read (ping-pong banks) (2/2) (burst length = 8, /cas latency = 3) clk cke /cs /ras /cas /we ba0 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l hi-z qba1 qba2 qba3 qba4 qba5 qba6 qba7 qba8 qaa1 qaa2 qaa3 qaa4 qaa5 h rbb rba cbb caa cba rbb raa rba raa qaa6 qaa7 ba1 activate command for bank b read command for bank b activate command for bank a read command for bank a precharge command for bank b activate command for bank b read command for bank b precharge command for bank a data sheet e0031n30 59 pd45128441, 45128841, 45128163 13.15 random row write (ping-pong banks) (1/2) (burst length = 8, /cas latency = 2) clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l hi-z daa5 daa6 daa7 daa8 dda1 dda2 dda3 dda4 dda5 dda6 dda7 dda8 dab1 h raa cab cda caa rda raa rda dab2 dab3 ba0 rab rab daa1 daa2 daa3 daa4 activate command for bank a write command for bank a write command for bank d activate command for bank d precharge command for bank a activate command for bank a write command for bank a precharge command for bank d data sheet e0031n30 60 pd45128441, 45128841, 45128163 random row write (ping-pong banks) (2/2) (burst length = 8, /cas latency = 3) clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 daa3 daa4 daa5 daa6 daa7 daa8 dda1 dda2 dda3 dda5 dda6 dda7 h raa cab cda rda raa rda dda8 dab1 dab2 rab daa1 daa2 ba0 caa rab activate command for bank a write command for bank a write command for bank d activate command for bank d precharge command for bank a activate command for bank a precharge command for bank d write command for bank a l hi-z dda4 data sheet e0031n30 61 pd45128441, 45128841, 45128163 13.16 read and write (1/2) (burst length = 4, /cas latency = 2) clk cke /cs /ras /cas /we ba1 a10 add dqm dq activate command for bank a read command for bank a write command for bank a 0-clock latency 2-clock latency read command for bank a t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 qaa1 qaa2 qaa3 qaa4 dab1 dab2 qac1 qac2 qac4 h raa cac cab dab4 ba0 caa write latency = 0 raa word masking l hi-z hi-z at the end of wrap function data sheet e0031n30 62 pd45128441, 45128841, 45128163 read and write (2/2) (burst length = 4, /cas latency = 3) clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 qaa1 qaa2 qaa3 qaa4 dab1 dab2 qac1 qac2 h raa cac cab dab4 caa raa ba0 activate command for bank a read command for bank a write command for bank a 0-clock latency read command for bank a word masking write latency = 0 l hi-z hi-z at the end of wrap function 2-clock latency data sheet e0031n30 63 pd45128441, 45128841, 45128163 13.17 interleaved column read cycle (1/2) (burst length = 4, /cas latency = 2) clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l hi-z aa1 aa2 aa3 aa4 da1 da2 dc1 dc2 dd1 dd2 dd3 dd4 h raa rda ab1 ab2 db1 db2 ba0 raa rda caa cda cdb cdc cab cdd activate command for bank a activate command for bank d read command for bank d read command for bank d read command for bank d read command for bank a read command for bank d precharge command for bank a precharge command for bank d read command for bank a data sheet e0031n30 64 pd45128441, 45128841, 45128163 interleaved column read cycle (2/2) (burst length = 4, /cas latency = 3) clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l hi-z aa1 aa2 aa3 aa4 da1 da2 dc1 dc2 ab3 ab4 h ab1 ab2 db1 db2 raa rda ba0 raa cab cdc rda cda caa activate command for bank a activate command for bank d read command for bank d read command for bank d read command for bank d read command for bank a precharge command for bank d precharge command for bank a read command for bank a cdb data sheet e0031n30 65 pd45128441, 45128841, 45128163 13.18 interleaved column write cycle (1/2) (burst length = 4, /cas latency = 2) clk cke /cs /ras /cas /we ba0 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l hi-z aa1 aa2 aa3 aa4 ba1 ba2 bc1 bc2 bd1 bd2 bd3 bd4 h raa rba ab1 ab2 bb1 bb2 raa rba caa cba cbb cbc cab cbd ba1 activate command for bank a write command for bank a activate command for bank b write command for bank b write command for bank a precharge command for bank a precharge command for bank b write command for bank b write command for bank b write command for bank b data sheet e0031n30 66 pd45128441, 45128841, 45128163 interleaved column write cycle (2/2) (burst length = 4, /cas latency = 3) clk cke /cs /ras /cas /we ba0 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l hi-z aa1 aa2 aa3 aa4 ba1 ba2 bc1 bc2 bd1 bd2 h ab1 ab2 bb1 bb2 raa rba raa cab cbc rba cba cbb caa cbd bd3 bd4 activate command for bank a write command for bank a activate command for bank b write command for bank b write command for bank a precharge command for bank a precharge command for bank b write command for bank b write command for bank b write command for bank b ba1 data sheet e0031n30 67 pd45128441, 45128841, 45128163 13.19 auto precharge after read burst (1/2) (burst length = 4, /cas latency = 2) clk cke /cs /ras /cas /we ba0 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l h ba1 rdb rac rda raa raa cab caa rdb cda rda cac cdb rac hi-z activate command for bank a activate command for bank d read command for bank a read with auto precharge command for bank d read with auto precharge command for bank a auto precharge start for bank d read with auto precharge command for bank d auto precharge start for bank a auto precharge start for bank d activate command for bank a read with auto precharge command for bank a activate command for bank d data sheet e0031n30 68 pd45128441, 45128841, 45128163 auto precharge after read burst (2/2) (burst length = 4, /cas latency = 3) clk cke /cs /ras /cas /we ba0 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l h rdb raa raa cab caa rdb cda rda cdb hi-z ba1 rda activate command for bank a activate command for bank d read command for bank a read with auto precharge command for bank d read with auto precharge command for bank a read with auto precharge command for bank d auto precharge start for bank d activate command for bank d auto precharge start for bank a data sheet e0031n30 69 pd45128441, 45128841, 45128163 13.20 auto precharge after write burst (1/2) (burst length = 4, /cas latency = 2) clk cke /cs /ras /cas /we ba0 a10 add dqm dq activate command for bank a write command for bank a activate command for bank d activate command for bank d write with auto precharge command for bank d write with auto precharge command for bank d write with auto precharge command for bank a auto precharge start for bank d auto precharge start for bank a auto precharge start for bank d activate command for bank a write with auto precharge command for bank a t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l h rdb rac rda raa raa cab caa rdb cda rda cac cdb rac ba1 hi-z data sheet e0031n30 70 pd45128441, 45128841, 45128163 auto precharge after write burst (2/2) (burst length = 4, /cas latency = 3) clk cke /cs /ras /cas /we ba0 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l h rdb raa raa cab caa rdb cda rda cdb rda ba1 hi-z activate command for bank a write command for bank a activate command for bank d write with auto precharge command for bank d write with auto precharge command for bank a auto precharge start for bank d auto precharge start for bank a activate command for bank d write with auto precharge command for bank d data sheet e0031n30 71 pd45128441, 45128841, 45128163 13.21 full page read cycle (1/2) (/cas latency = 2) clk cke /cs /ras /cas /we ba0 a10 add dqm dq t0 t1 t2 t3 t4 t5 t7 tn tn + 1tn + 2tn + 3tn + 4tn + 5tn + 6tn + 7tn + 8tn + 9tn + 10 tn + 11 tn + 12 tn + 13 h raa rda rdb raa rda cda caa rdb aa aa+1 aa+2 aa-2 aa-1 aa aa+1 da da+1 da+2 da+3 da+4 da+5 da+6 activate command for bank a read command for bank a activate command for bank d read command for bank d burst stop command precharge command for bank d activate command for bank d t6 ba1 l hi-z data sheet e0031n30 72 pd45128441, 45128841, 45128163 full page read cycle (2/2) (/cas latency = 3) clk cke /cs /ras /cas /we ba0 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 tn tn + 1tn + 2tn + 3tn + 4tn + 5tn + 6tn + 7tn + 8tn + 9tn + 10 tn + 11 tn + 12 l h raa rda rdb raa rda cda caa rdb aa aa+1 aa-3 aa-2 aa-1 aa aa+1 da da+1 da+2 da+3 da+4 da+5 precharge command for bank d activate command for bank a read command for bank a activate command for bank d read command for bank d burst stop command activate command for bank d hi-z ba1 data sheet e0031n30 73 pd45128441, 45128841, 45128163 13.22 full page write cycle (1/2) (/cas latency = 2) clk cke /cs /ras /cas /we ba0 a10 add dqm dq t0 t1 t2 t3 t4 t5 tn tn + 1tn + 2tn + 3tn + 4tn + 5tn + 6tn + 7tn + 8tn + 9tn + 10 tn + 11 tn + 12 tn + 13 tn + 14 tn + 15 h raa rda rdb raa rda cda caa rdb aa aa+1 aa+2 aa-2 aa-1 aa aa+1 da da+1 da+2 da+3 da+4 da+5 ba1 precharge command for bank d activate command for bank a write command for bank a activate command for bank d write command for bank d burst stop command activate command for bank d l hi-z data sheet e0031n30 74 pd45128441, 45128841, 45128163 full page write cycle (2/2) (/cas latency = 3) clk cke /cs /ras /cas /we ba0 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 tn tn + 1tn + 2tn + 3tn + 4tn + 5tn + 6tn + 7tn + 8tn + 9tn + 10 tn + 11 tn + 12 tn + 13 h raa rda rdb raa rda cda caa rdb aa aa+1 aa+2 aa+3 aa-1 aa aa+1 da da+1 da+2 da+3 da+4 da+5 precharge command for bank d activate command for bank a write command for bank a activate command for bank d burst is not completed in the full page mode write command for bank d burst stop command activate command for bank d ba1 l hi-z data sheet e0031n30 75 pd45128441, 45128841, 45128163 13.23 byte write operation (burst length = 4, /cas latency = 2) clk cke /cs /ras /cas /we ba0 a10 add ldqm t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 udqm ba1 dq (lower) dq (upper) activate command for bank d read command for bank d upper byte not read lower byte not write upper byte not write lower byte not write data sheet e0031n30 76 pd45128441, 45128841, 45128163 byte write operation (burst length = 4, /cas latency = 3) clk cke /cs /ras /cas /we ba0 a10 add ldqm t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 udqm ba1 dq (lower) dq (upper) activate command for bank d read command for bank d read command for bank d upper byte not read lower byte not read lower byte not read lower byte not read lower byte not write upper byte not write lower byte not write data sheet e0031n30 77 pd45128441, 45128841, 45128163 13.24 burst read and single write (option) (burst length = 4, /cas latency = 2) clk cke /cs /ras /cas /we ba0 a10 add dqm t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 h hi-z dq ba1 activate command for bank d read command for bank d single write command for bank d single write command for bank d read command for bank d single write command for bank d qa1 qa2 qa3 qa4 d1 qb1 qb2 qb4 d2 data sheet e0031n30 78 pd45128441, 45128841, 45128163 burst read and single write (option) (burst length = 4, /cas latency = 3) clk cke /cs /ras /cas /we ba0 a10 add dqm t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 h hi-z dq ba1 activate command for bank d read command for bank d single write command for bank d single write command for bank d read command for bank d qa1 qa2 qa3 qa4 d1 qb1 qb2 qb4 data sheet e0031n30 79 pd45128441, 45128841, 45128163 13.25 full page random column read (burst length = full page, /cas latency = 2) clk cke /cs /ras /cas /we ba0 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l h hi-z raa cac cdb cab rda rda cdc raa ba1 caa cda qaa1 qda1 qab1 qab2 qdb1 qdb2 qac1 qac2 qac3 qdc1 qdc2 qdc3 activate command for bank a activate command for bank d read command for bank a read command for bank d read command for bank a read command for bank d read command for bank a read command for bank d precharge command for bank d (pre termination of burst) data sheet e0031n30 80 pd45128441, 45128841, 45128163 full page random column read (burst length = full page, /cas latency = 3) clk cke /cs /ras /cas /we ba0 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l h hi-z raa cac cdb cab rda rda cdc raa ba1 caa cda qaa1 qda1 qab1 qab2 qdb1 qdb2 qac1 qac2 qac3 qdc1 qdc2 qdc3 activate command for bank a activate command for bank d read command for bank a read command for bank d read command for bank a read command for bank d read command for bank a read command for bank d precharge command for bank d (pre termination of burst) hi-z data sheet e0031n30 81 pd45128441, 45128841, 45128163 13.26 full page random column write (burst length = full page, /cas latency = 2) clk cke /cs /ras /cas /we ba0 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l h hi-z raa cac cdb cab rda rda cdc raa ba1 caa cda daa1 dda1 dab1 dab2 ddb1 ddb2 dac1 dac2 dac3 ddc1 ddc2 ddc3 ddc4 precharge command for bank d (pre termination of burst) activate command for bank a activate command for bank d write command for bank a write command for bank d write command for bank a write command for bank d write command for bank a write command for bank d data sheet e0031n30 82 pd45128441, 45128841, 45128163 full page random column write (burst length = full page, /cas latency = 3) clk cke /cs /ras /cas /we ba0 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l h hi-z raa cac cdb cab rda rda cdc raa ba1 caa cda daa1 dda1 dab1 dab2 ddb1 ddb2 dac1 dac2 dac3 ddc1 ddc2 ddc3 ddc4 precharge command for bank d (pre termination of burst) activate command for bank a activate command for bank d write command for bank a write command for bank d write command for bank a write command for bank d write command for bank a write command for bank d data sheet e0031n30 83 pd45128441, 45128841, 45128163 13.27 pre (precharge) termination of burst (1/2) (burst length = 8, /cas latency = 2) clk cke /cs /ras /cas /we ba0 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l h ba1 hi-z raa rab caa raa rab cab daa1 daa2 daa3 daa4 daa5 qab1 qab2 qab3 qab4 qab5 activate command for bank a activate command for bank a write command for bank a pre termination of burst pre termination of burst precharge command for bank a activate command for bank a read command for bank a precharge command for bank a hi-z write masking rac rac t rcd t dpl t rp t ras t ras data sheet e0031n30 84 pd45128441, 45128841, 45128163 pre (precharge) termination of burst (2/2) (burst length = 8, /cas latency = 3) clk cke /cs /ras /cas /we ba0 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l hi-z h ba1 raa rab caa raa rab cab daa1 daa2 daa3 qab1 qab2 qab3 qab4 hi-z activate command for bank a activate command for bank a write command for bank a pre termination of burst precharge command for bank a precharge command for bank a activate command for bank a read command for bank a pre termination of burst daa4 daa5 write masking rac rac t rcd t rp t ras t dpl t ras data sheet e0031n30 85 pd45128441, 45128841, 45128163 14. package drawing notes 1. each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. 2. dimension "a" does not include mold fiash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side. m p a g c n b m d l k j h i e f detail of lead end s 54 28 127 s item b c i l m n 54-pin plastic tsop ( ii ) (10.16 mm (400)) a d e f g h j p millimeters 0.80 (t.p.) 0.91 max. 0.13 0.50 0.10 10.16 0.10 0.10 22.22 0.05 0.10 0.05 0.32 1.1 0.1 11.76 0.20 1.00 + 0.08 ? 0.07 0.80 0.20 3 + 7 ? 3 k 0.145 + 0.025 ? 0.015 s54g5-80-9jf-2 data sheet e0031n30 86 pd45128441, 45128841, 45128163 15. recommended soldering conditions please consult with our sales offices for soldering conditions of the pd45128xxx. type of surface mount device pd45128xxxg5 : 54-pin plastic tsop (ii) (10.16mm (400)) data sheet e0031n30 87 pd45128441, 45128841, 45128163 16. revision history edition / page description date this edition previous edition type of revision location nec corporation (m12650e) 9th edition / mar. 1999 p.15 p.15 modification, addition cke truth table - power down p.19 p.19 modification, addition command truth table for cke - power down p.35 p.35 modification i cc1 (spec), i cc2 ns (spec), i cc3 n (spec), i cc4 (spec), i cc5 (spec) p.37 p.37 modification output load p.50 p.50 modification timing chart (power down mode and clock mask) p.77 p.77 modification timing chart (full page random column read) 10th edition / throughout throughout modification a13 ba0, a12 ba1 jan. 2000 p.2, 3 p.2, 3 addition -a75 deletion -axxl (low power) p.34 p.34 addition pin capacitance (max.) p.35 p.35 addition -a75 specs modification i cc5 deletion i cc6 -axxl (low power) p.36 p.36 modification ac characteristics test conditions p.37, 38, 42 p.37, 38, 42 addition -a75 specs p.76, 78, 80, 82 ? addition timing chart (/cas latency = 3) p.85 p.81 modification package drawing 11th edition / p.38 p.38 modification t rc1 spec (-a10) apr. 2000 elpida memory, inc. (e0031n) 1st edition / jan. 2001 ? ? ? republished by elpida memory, inc. ver. 2.0 / june 2001 p.2, 3 p.2, 3 addition -axxl (low power) p.2, 3, 35, 37, 38, 42 p.2, 3, 35, 37, 38, 42 deletion -10b specs p.35 p.35 addition i cc6 -axxl (low power) ver. 3.0 / p.2, 3 p.2, 3 addition -a75a and -a75al (low power) august 2001 p.35, 37, 38 p.35, 37, 38 addition -a75a specs data sheet e0031n30 88 pd45128441, 45128841, 45128163 [memo] data sheet e0031n30 89 pd45128441, 45128841, 45128163 [memo] data sheet e0031n30 90 pd45128441, 45128841, 45128163 [memo] data sheet e0031n30 91 pd45128441, 45128841, 45128163 notes for cmos devices 1 precaution against esd for mos devices exposing the mos devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the mos devices operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. mos devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. mos devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor mos devices on it. 2 handling of unused input pins for cmos devices no connection for cmos devices input pins can be a cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. the unused pins must be handled in accordance with the related specifications. 3 status before initialization of mos devices power-on does not necessarily define initial status of mos devices. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the mos devices with reset function have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. mos devices are not initialized until the reset signal is received. reset operation must be executed immediately after power-on for mos devices having reset function. cme0107 pd45128441, 45128841, 45128163 m01e0107 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of elpida memory, inc. elpida memory, inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of elpida memory, inc. or third parties by or arising from the use of the products or information listed in this document. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of elpida memory, inc. or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. elpida memory, inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [product applications] elpida memory, inc. makes every attempt to ensure that its products are of high quality and reliability. however, users are instructed to contact elpida memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [product usage] design your application so that the product is used within the ranges and conditions guaranteed by elpida memory, inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. elpida memory, inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating elpida memory, inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the elpida memory, inc. product. [usage environment] this product is not designed to be resistant to electromagnetic waves or radiation. this product must be used in a non-condensing environment. if you export the products or technology described in this document that are controlled by the foreign exchange and foreign trade law of japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of japan. also, if you export products/technology controlled by u.s. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. if these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. the information in this document is subject to change without notice. before using this document, confirm that this is the late st version. |
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